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Name: perlilog
Created: Jan 16, 2004
Updated: Mar 6, 2004
SVN Updated: Mar 10, 2009

Other project properties

Category: Other
Development status: Beta
Additional info:
WishBone Compliant: No


Perlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs.
At a smaller scale, Perlilog is a great starting point for writing scripts which handle Verilog code in general. It comes with a rich set of functions, that can be used for several purposes, such as instantiation of ASIC pads, automatic connection and generation of simple Verilog modules, and so on.
The philosophy behind Perilog is that an IP core should be like a black box. Fitting it for a certain purpose should be as easy as defining the desired requirements. Connecting the cores, to become a system, should be as easy as drawing a block diagram.
With plain Verilog, the reality couldn't be further away. But by using Perlilog correctly, integration can be that simple.
Perlilog introduces a new meaning to "IP core". It also introduces a different way to approaching the task of interfacing cores with each other.
Perlilog was built to make core programming and integration intuitive tasks. As such, it is based on new, rather natural concepts, which one must get used to in order to gain the most of the tool.
Perlilog is written in Perl, currently with no GUI. While the scripts, that the system consists of, are rather sophisticated, only plain Perl knowledge is needed to use its scripting capabilities.

Bye bye Verilog?

Absolutely not. Verilog is still the language to define the functionality of the core. The final output of a design, which incorporates Perlilog, is perfectly normal Verilog files.
Perlilog will do the following tasks instead of you:
- Instantiation of modules
- Connection between modules
- Setting up modules' attributes (word width, address mapping on buses etc.)

Status of the project

The current version is highly usable for general scripts, which involve Verilog code. As for sophisticated SoC generation, it still lacks script pieces, which makes it directly useful to connect real-life cores.
The project is known to be used by a few Verilog designers, and despite the official "beta" stage, no significant bugs have been found. The project appears to be reliable.
Features are added to Perlilog whenever the system is shown to be incapable of meeting a reasonable need. Those who want to try Perlilog are encouraged to contact the maintainer directly.
The project comes with a guide, which includes all knowledge needed to enrich the tool, so it can connect real-life IP cores as promised above.


The Perlilog project is maintained by its author, Eli Billauer. He can be reached at elib@flextronics.co.il.
The project and its documentation can be downloaded by clicking the "Downloads"
tag on the navigation bar on the top of this page.