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Source code


Name: parallelcrcgen
Created: Jul 10, 2009
Updated: Jul 30, 2014
SVN Updated: May 1, 2011

Other project properties

Category: Other
Language: C/C++
Development status: Stable
Additional info: Specification done
WishBone Compliant: No
License: LGPL


  CRC Generator is a command-line application that generates Verilog or VHDL code for a parallel CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The CRC can be custom or protocol specific, for example PCI Express, USB5, USB16, 802.3, SATA.
  The code is written in C and is cross-platform compatible
  There is an online version of the tool at OutputLogic.com
It's more convenient to access, but the online tool is slower to generate the code for CRC with large data and polynomial widths.