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Source code


Name: datetime
Created: Jun 15, 2012
Updated: Jun 17, 2012
SVN Updated: Jun 17, 2012

Other project properties

Category: Other
Language: Verilog
Development status: Planning
Additional info:
WishBone Compliant: No
License: LGPL


This is a date/time keeping core. It uses an external 100,60 or 50 Hz time-of-day signal to update a group of BCD counters which record the date and time. The date and time is presented as a 16 digit BCD format YYYYMMDDHHMMSSJJ which fits into a 64-bit word.


- optional 50,60, or 100 Hz time-keeping
- 64 bit bus interface
- internally decoded to respond in address range $DC0400-$DC0418
- Mars timekeeping option (millennium style calendar)
- leap year tracking
- independent system bus and time-of-day clocks
- alarm setting