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Source code


Name: cdc_ufifo
Created: Dec 2, 2010
Updated: Jan 28, 2011
SVN Updated: Dec 2, 2010

Other project properties

Category: Other
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
License: BSD


Clock Domain Crossing micro FIFO (Verilog/SystemVerilog):
cdc_ufifo provide an minimalist fifo. Most advantage - not use RAM blocks.
it can be 4 buffer data cells minimum.
by default used implementation without ram, only standart register cells used, and it can be selected if need. most slowest stage is the output multiplexor
Shadowed outputs: provide an register after multiplexer to remove data unsynchronized changes from outputs when skiped some cycles.


CycloneII project works on up to 50 MHz data transfers