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Source code


Name: sudoku
Created: Sep 4, 2013
Updated: Sep 5, 2013
SVN Updated: Nov 19, 2013

Other project properties

Category: Other
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL


Simple backtracking 9x9 Sudoku solver written in Verilog. Uses an exact cover algorithm to quickly find a solution with minimal backtracking (C implementation of algorithm provided too).
High wiring complexity due to explicit "neighbor" interconnect (row, column, and 3x3 sub-block) may result in unroutable designs on FPGA families with reduced routing resources.
Working on an Zynq XC702 FPGA.