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Source code


Name: freq_div
Created: May 9, 2010
Updated: Mar 3, 2011
SVN Updated: Jul 23, 2010

Other project properties

Category: Other
Language: Verilog
Development status: Stable
Additional info: ASIC proven , Design done , Specification done
WishBone Compliant: No
License: LGPL

Usage and Operation

In order to operate the circuit correctly it must first be reset (asynchronously). Below is a timing diagram that illustrates the reset pulse timing requirements.
Note: the circuit only needs to be reset once to operate properly. Every time the divide factor N changes, the circuit automatically resets itself. Suggested Timing Diagram


The adjustable frequency divider is designed in two parts:

  1. Even Divider
  2. When the input signal 'N' is set to an even number the even divider is used because the output will be synchronized with the rising edges of the input clock. The even divider has a much simpler architecture consisting of basically cascaded flip-flops.
  3. Odd Divider
  4. When 'N' is odd the output needs to be synchronized with both the rising and falling edges of the input clock in order to achieve a 50% duty cycle output. The odd divider is much more complex than the even divider and requires two internal counters that are offset from each other.
Top Level Block Diagram