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Source code


Name: wb_async_mem_bridge
Created: Nov 18, 2009
Updated: Dec 4, 2009
SVN Updated: Mar 29, 2011

Other project properties

Category: Memory core
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: Yes
License: LGPL


This project provides a bridge between asynchronous external memory interfaces found on many processors and a WishBone bus. It is being used on the de1_olpcl2294_system project.