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Source code


Name: wb2mig
Created: Apr 6, 2011
Updated: Apr 7, 2011
SVN Updated: Apr 7, 2011

Other project properties

Category: Memory core
Language: Verilog
Development status: Planning
Additional info:
WishBone Compliant: Yes
License: LGPL


Two WISHBONE wrappers will be developed for Xilinx Memory Interface Generator (MIG). The first is compliant with version B4 Registered Feedback Incrementing Burst Cycle. The second is a non-compliant but streamlined interface developed as a proposal for inclusion as a new Burst Cycle Type geared towards interfacing with high latency devices.