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Source code


Name: wb_fifo
Created: Jun 8, 2014
Updated: Feb 16, 2015
SVN Updated: May 12, 2015

Other project properties

Category: Memory core
Language: VHDL
Development status: Beta
Additional info:
WishBone Compliant: No
License: LGPL


A very generic implementation of a FIFO. Makes good use of VHDL transactors for data transfers.