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Source code


Name: dpsfmnce
Created: Nov 1, 2013
Updated: Nov 2, 2013
SVN Updated: Nov 2, 2013

Other project properties

Category: Memory core
Language: Verilog
Development status: Mature
Additional info: Design done , FPGA proven
WishBone Compliant: No
License: LGPL


This project provides a parameterizable synchronous FIFO which uses LUTs instead of Block RAMs for its memory. The FIFO can be parameterized in depth and width. It has been used in a number of commercial products. It is primarily used for implementing small buffers for the transmit and receive functions of UARTs. (A companion project, BRSFmnCE, provides the same basic functionality using block RAMs.)

Synthesis/PAR Summary

The DPSFmnCE has been used in several projects/products. It is generally used as a small FIFO for UARTs. The following synthesis and Map/PAR results effectively summarize the resource utilization of the DPSFmnCE in a XC3S50A-4VQG100I FPGA. This FPGA is not the only one in which DPSFmnCE has been used, but it allows the characterization of the resource requirements of the DPSFmnCE.
Results for 16 x 8 Distributed RAM Synchronous FIFO
Number of Occupied Slices: 32
Number of Slice FFs: 14
Number of 4-input LUTs: 52
Number used a Logic: 20
Number used as RAMs: 32
Reported Speed (Synthesizer): 276 MHz
Reported Speed (MAP/PAR): 252 MHz