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Source code


Name: cachecontroller
Created: Jan 5, 2010
Updated: Jan 7, 2010
SVN Updated: Jan 7, 2010

Other project properties

Category: Memory core
Language: Verilog
Development status: Mature
Additional info:
WishBone Compliant: No
License: LGPL


This project is to develop a direct mapped cache controller for embedded applications.
Key Design Features
- Direct mapped with configurable address size, line size and number of cache lines
- Non Pipelined architecture
- No Cache flush
Synthesis will be conducted using VirtexII Pro


7th January 2010
Memory(RAM) implementation completed