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Source code


Name: ddr3_synthesizable_bfm
Created: Nov 30, 2011
Updated: Dec 3, 2011
SVN Updated: Dec 4, 2011

Other project properties

Category: Memory core
Language: Verilog
Development status: Beta
Additional info: Design done
WishBone Compliant: No
License: LGPL


This is a fully synthesizable DDR3 Memory BFM. Implemented using Verilog 2001 without any vendor specific IP Block. As such, the BFM is not able to run a very high speed. Test shown that is is able to respond to WRITE and READ instruction at 10MHz.


Memory BFM has been tested and passes all Micron DDR3 testbench. It is also has been tested and able to passes Altera DDR3 Testbench.Has been synthesized using Xilinx ISE 13.2 and Quartus II Version 11.1 Build 173