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Source code


Name: extension_pack
Created: Jan 6, 2006
Updated: Oct 25, 2010
SVN Updated: Mar 10, 2009

Other project properties

Category: Library
Language: VHDL
Development status: Stable
Additional info: Design done
WishBone Compliant: No


This project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code.


automatic count stop/start value generation functions. You enter a time duration and clock frequency and the value is automatically computed. Your choice of binary or LFSR number spaces.
LFSR counters created by function call.
clock generation procedures
type and number conversion functions:
synthesizable binary_to_BCD and BCD_to_binary functions
synthesizable BCD_to_seven_segment display functions
string value to std_logic_vector: "32" -> "0100000"


Production Ready. Please let me know of ANY problems you find.

Project Type

VHDL Library