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Source code


Name: robust_fir
Created: Mar 23, 2011
Updated: Jun 18, 2012
SVN Updated: Jul 3, 2011

Other project properties

Category: DSP core
Language: Verilog
Development status: Stable
Additional info:
WishBone Compliant: No
License: LGPL


Generic FIR filter. Builds optimized filter according to number of multipliers, supports serial or parallel architecture. Supports delays in input. Builds Verilog FIR filter according to input parameters: multiplier number, filter order, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools