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Source code


Name: wdsp
Created: Dec 13, 2011
Updated: Mar 17, 2014
SVN Updated: Mar 17, 2014

Other project properties

Category: DSP core
Language: VHDL
Development status: Alpha
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: Yes
License: LGPL


WDSP project includes three System on Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR filter core is based on the transpose realization form, the IIR filter core is based on the Second Order Sections (SOS) architecture and the FFT core is based on the Radix 2^2 Single Delay Feedback (R2^2SDF) architecture. The three cores are compatible with the Wishbone SoC bus and they were described using generic and structural VHDL. In system hardware verification was performed by using MinSoC synthesized on an Altera FPGA, the tests showed that the designed DSP cores are suitable for building SoC based on the OpenRisc processor and the Wishbone bus.