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Source code


Name: cascaded_fir_filter
Created: May 21, 2015
Updated: Jun 16, 2015
SVN Updated: May 25, 2015

Other project properties

Category: DSP core
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL


FIR filter
- architecture written with pure verilog
- parameterizable in verilog code
- cascaded - processing is paralleled
- data and coefficients stored in RAM - suitable for long pulse response FIR and limited registers count
- complex data
- fixed point
* load coefficient from input data as option - for echo/sonar/radar/etc processing

FPGA resources using

Altera Cyclone IV E EP4CE22E22C8

Parameters of filter
Input data width 14 b, 2 channels
Pulse response length 2048 samples
Cell size 1024 (2 cells for 2048 samples used)
Output data width 28 b, 2 channels

Resources usage
Total logic elements 840
- Total combinational functions 558
- Dedicated logic registers 537
Total registers 537
Total memory bits 114,688
Embedded Multiplier 9-bit elements 20