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Source code


Name: canny_edge_detector
Created: Jun 9, 2014
Updated: Oct 29, 2014
SVN Updated: Jun 9, 2014

Other project properties

Category: DSP core
Language: VHDL
Development status: Beta
Additional info: Design done , FPGA proven
WishBone Compliant: No
License: LGPL


Canny edge detector with a 9x9 mask (gradient + gaussian filtering with sigma = sqrt(2)). Able to produce a throughput of 1 pixel per clock cycle. Succesfully implemented on a Virtex4 up to 300Mhz clock frequency.