Created: Sep 25, 2001
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
WishBone Compliant: No
- IIR filter with two poles and two zeros
- Data width set by user
- Coefficient width set by user up to 16 bits
- Wishbone interface for read and write of filter coefficient registers
- Multiple filters can be combined to form filters with more than two poles and zeros
The difference equation for the biquad filter is:
y[n] = b10*x[n] + b11*x[n-1] + b12*x[n-2] + a11*y[n-1] + a12*y[n-2]
This equation is implemented as shown below:
Synthesized with Synopsys FPGA Express version 2000.11-FE3.5.
If you use this core please let me know.