Go Back

Source code


Name: rc4-prbs
Created: May 17, 2012
Updated: Feb 26, 2013
SVN Updated: Jun 2, 2013

Other project properties

Category: Crypto core
Language: Verilog
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
License: LGPL


RC4 PRBS (Generates the RC4 stream, then you have to XOR it with your data to crypt or decrypt it), takes 768 clocks to do key-expansion, then start outputting one-byte of random stream for every clock (output_read signals valid output in K). Based on RC4 implementation in wikipedia.