Go Back

Source code


Name: gost28147
Created: Apr 17, 2012
Updated: Jun 2, 2015
SVN Updated: Mar 19, 2014

Other project properties

Category: Crypto core
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
License: BSD


This is a implementation of the GOST 28147-89 - a Soviet and Russian government standard symmetric key block cipher.
GOST 28147-89 has a 64-bit blocksize and 256-bit keysize.
This implementation provide trade off size and performance. The goal was to be able to fit in to a low cost Xilinx Spartan series FPGA and still be as fast as possible. As one can see from the implementation results below, this goal has been achieved.


- SystemVerilog RTL and TB code is provided
- Implements both encryption and decryption in the same block
- GOST 28147-89 algorithm focusing on very low area applications
- Implementation takes about 32 cycles to encrypt/decrypt a block
- EBC-cipher mode support
- The core complies to use of S-box according to RFC4357/GOST R34.11-94 or RFC5830 (by synthesis), or S-box switch "on the fly" (realtime).


- Core implementations have been tested on a Xilinx Spartan-3E FPGA succesfully
- This core is done. Initial Release: Apr. 17, 2012


For run synthesize design using Synplify tool use command:

      $ make synthesis
To compile and run simulation RTL-design using ModelSim with CLI:
      $ make sim
To compile and run simulation RTL-design using ModelSim with GUI:
      $ make sim-gui
In order to determine which S-box will be used for synthesis/simulation you must to pass apropriate define by command line argument:
      - for RFC4357 S-box using
      - for RFC5830 S-box using
      - both RFC4357 and RFC5830 S-boxes using with switching "on the fly"
All procedures like synthesis or simulation was tested on the Linux environment (x86_64 host).


Sample Synthesis Results for the ECB-mode GOST 28147-89

      Technology 	       Size/Area 	Speed/Performance
Xilinx Spartan-3E      525 LUTs         75 Mhz (150 Mbits/sec)


The design uses SystemVerilog as language for RTL-implementation therefore your Design Tools should support SystemVerilog for synthesis and simulation.


- Implementation testing with support Botan crypto-lib. It can be used in a DPI-based testbench as golden model or test vector generator
- Support for following cipher modes: CBC, CFB, OFB (and maybe CTR)
- Adding SoC-buses compatibility for seamless integration


- Description of GOST 28147-89 [ENGLISH]
- Description of GOST 28147-89 [RUSSIAN]