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Source code


Name: bluespec_md6
Created: Aug 6, 2008
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009

Other project properties

Category: Crypto core
Language: Other
Development status: Beta
Additional info: FPGA proven
WishBone Compliant: No


- Latency insensitive design
- Should be portable to most bus architectures/platforms
- Easily amenable to multi-clock domain extension
- Support for long burst transfers
- Configurable number of compression cores, compression core parallelism


This project is under on-going development as we seek to explore and to improve the architecture of the implementation.
We have demonstrated this architecture on the Xilink XUP board, on which we have obtained throughputs in excess of 233 MB/s for MD6-512