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Source code


Name: aes-128_pipelined_encryption
Created: Sep 7, 2013
Updated: Apr 3, 2015
SVN Updated: Sep 9, 2013

Other project properties

Category: Crypto core
Language: Verilog
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
License: LGPL


The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts data to an unintelligible form called ciphertext .Here the AES algorithm is capable of using cryptographic keys of 128bit to do this conversion .This module is optimized for speed as it pipeline hardware to perform repeated sequence called round. This module synthesized on Xilinx virtex 6 6vcx240tff784-2 board using ISE. Fuctional and gate level simulation were done using AES validation suite (AESVS) vectors


-128 bit data
-128 bit Cipher Key
-One Clock domain
-Optimized for speed
-Pipelined architecture
-Generic RTL (vendor independent)