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Source code


Name: wishbone_uart_controller
Created: May 26, 2013
Updated: May 27, 2013
SVN Updated: May 28, 2013

Other project properties

Category: Communication controller
Language: VHDL
Development status: Beta
Additional info:
WishBone Compliant: No
License: LGPL


this core work whit uart.
it is used to communicate as a wishbone master, it also contains slaves.
these slaves are made to be a bridge between wishbone bus and I/O modules.
the slaves handle the wishbone signal , addresses etc.
it can be modded to work for an 8 bit processor.
instruction set based.