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Source code


Name: wb_uart
Created: Oct 11, 2009
Updated: Feb 14, 2010
SVN Updated: Oct 12, 2009

Other project properties

Category: Communication controller
Language: VHDL
Development status: Beta
Additional info:
WishBone Compliant: Yes
License: LGPL


Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt.
Please find there the documentation regarding the Uart core.
The interface is now compatible with a 8-bit WishBone bus.
With GHDL simulator simply run:
Using any other simulator, before starting the simulation the following perl script must be run:
uart_test_stim.pl > filename.txt
where filename.txt is the name selected in generic "stim_file" inside wb8_uart_transactor.vhd.
A correct simulation should exit with an assertion message "simulation END".
This IP is provided by IPdesign (www.ipdesign.eu).