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Source code


Name: usb_device_core
Created: Mar 26, 2014
Updated: Mar 27, 2014
SVN Updated: Mar 27, 2014

Other project properties

Category: Communication controller
Language: Verilog
Development status: Alpha
Additional info: Design done , FPGA proven
WishBone Compliant: Yes
License: LGPL


A simple full speed USB device core with 4 endpoints.
Comes with virtual COM port demo sw.
More details to follow.