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Source code


Name: uart2spi
Created: Jan 15, 2013
Updated: Jan 31, 2013
SVN Updated: Jan 31, 2013

Other project properties

Category: Communication controller
Language: Verilog
Development status: Mature
Additional info:
WishBone Compliant: No
License: LGPL


The UART to SPI IP Core include a simple command parser that can be used to access an internal bus of SPI via a UART interface. This IP can be used understand the SPI transaction protocol. The internal bus is designed with address bus of 16 bits and data bus of 8 bits. The core implements a very basic UART transmit & receive blocks which share a common baud rate generator and a command parser. The parser supports text mode of command parsing. Text mode commands are designed to be used with hyper terminal software and enable easy access to the internal bus.

Block Diagram

UART2SPI Block Diagram