Go Back

Source code


Name: tdm_switch
Created: May 3, 2003
Updated: Dec 19, 2013
SVN Updated: Mar 10, 2009

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info:
WishBone Compliant: No


The TDM_Switch core is a non-blocking digital switch that has a capacity of 256 x 256 channels at 2.048 Mb/s. Some of the main features are: Processor Mode and input offset delay.


- 256 x 256 channel non-blocking switching at 2.048 Mb/s
- Accept 8 serial data streams of 2.048 Mb/s
- Per-stream frame delay offset programming
- Connection memory block programming
- Microprocessor Interface


This IP core is synthesized for Xilinx SPARTAN-II series FPGA’s, fit at xc2s50-6tq144 device and the post place & route simulation model simulate with Cadence NC-Sim simulator.