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Source code


Name: spislave
Created: Dec 7, 2009
Updated: Mar 3, 2010
SVN Updated: Dec 19, 2009

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info:
WishBone Compliant: No
License: LGPL


spislave is a minimalist spislave IP core that provides the basic framework for the implementation of custom spislave devices. The core provides a means to write up to 256 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface. A full Icarus Verilog test bench is available.
Test it for yourself, using the free Icarus Verilog simulator and the free GTKWave wave form viewer.Download and install Icarus Verilog. -
Download and install GTKWave.
- Download the project files. - For executing the testbench just run the Makefile on the bench folder.
In GTKWave, use "Search >> Signal Search Tree" to view more waves.


- Standalone. No microprocessor required. For master side we need an microntroller
- Create your own custom spislave peripheral.
- Easily configurable for different input clock frequencies.
- Full Icarus Verilog test bench.
- This is to be tested with Our Zkit-51( 8 bit microcon board),a lcd(16x2) and Xilinx Spartan 3A FPGA board


- Tested in Zkit - 51 (8 bit microcontroller board) with Xilinx Spartan 3A FPGA board.
- Tested in simulation.
- Tested waveform in GTK wave.