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Source code


Name: spiadc
Created: Jun 14, 2009
Updated: Jun 23, 2009
SVN Updated: Jun 15, 2009

Other project properties

Category: Communication controller
Language: VHDL
Development status: Stable
Additional info: Design done
WishBone Compliant: No
License: LGPL

this core represents an minimalistic SPI receiver for ADC like AD747x.
one have:
- tunable sequence len, loaded data slice of sequence,
- shut-down short sequense generation
- ability continued sequence mode - without frame entry/completing
- ready output for locking received data
- shifht clock output provide ability to build parallel vector receivers by
adding needed shift registers
Syntesis on QuartusII 8.1 Web for EP1C3 16bit sequense with 10 loaded bit ocupies 31 cells