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Source code


Name: smbus_if
Created: May 9, 2003
Updated: Jan 22, 2004
SVN Updated: Mar 10, 2009

Other project properties

Category: Communication controller
Development status: Planning
Additional info:
WishBone Compliant: Yes


The System Management Bus (SMBus) is a two-wire interface through which simple system and power management related chips can communicate with the rest of a system. SMBus provides a control bus for system and power management related tasks. The SMBus is a multi-master bus, meaning that more than one device capable of controlling the bus can be connected to it. This core is based on the SMBus 2.0 specification, and utilizes its address resolution protocol using an 128-bit unique device identifier (UDID).


- SMBUS 2.0 Compliant
- 128-bit UDID
- Hardware packet error checking (PEC)
- Supports all SMBus ARP commands
- SMBus slave address is assignable
- Supports both SMBus Reset commands.
- SMBus arbiter allowing host/slave communication
- SMBus Clock synchronization/Clock Stretching
- WISHBONE B.3 SOC bus compatible


- Writing of initial specification is underway