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Source code


Name: sasc
Created: Sep 17, 2002
Updated: Mar 30, 2006
SVN Updated: Mar 10, 2009

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No


Simple asynchronous serial controller (aka UART). Includes 4
byte receive and a 4 byte transmit FIFO (FIFO size can be easily
adjusted). External baud rate generator (included). Very small.


- Implemented in Verilog
- Flow Control (CTS/RTS)
- 1 start bit, 1 stop bit, NO parity
- 4 byte receive FIFO
- 4 byte transmit FIFO
- Fully Synthesisable
- 102 LUTs in a Spartan II


This core is fully functional and completed.
It was verified in hardware in an XESS XVC800 FPGA prototype
board with a Maxim RS232 line driver.

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