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Source code


Name: sgmii
Created: Feb 8, 2012
Updated: Aug 1, 2014
SVN Updated: Nov 18, 2012

Other project properties

Category: Communication controller
Language: Verilog
Development status: Beta
Additional info: Design done
WishBone Compliant: No
License: GPL


Generic SGMII / 1000X module that can be connected to any transceiver technology.
This core has been verified with 88E1111 Phy
- Autonegotiation
- Rx & Tx in 1000Mbps mode
- Slow bit rate ~ 10Mbps
I don't have adequate tools to verify at full speed.
I appreciate any effort to verify and report bugs.
Everyone is welcome to try this core.
I can be contacted at jefflieu@fpga-ipcores.com for other license/support/bring-up issue. Btw, if you think it's useful to you, you can show your appreciation by donating to Paypal account: jefflieu@fpga-ipcores.com