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Source code


Name: sata_phy
Created: Jul 12, 2012
Updated: Mar 10, 2014
SVN Updated: Jul 12, 2012

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info:
WishBone Compliant: No
License: LGPL


SATA PHY layer which can be implemented as either a host or device for Xilinx 6 series devices.
A host controller core with AXI interface is available, contact me for more information.