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Source code


Name: xge_ll_mac
Created: Nov 15, 2012
Updated: Dec 1, 2012
SVN Updated: Dec 1, 2012

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info:
WishBone Compliant: No
License: LGPL


This is a fork of the xge_mac and was released by the Computer Architecture Group ( http://cag.uni-hd.de) of the University of Heidelberg.
Main changes in this fork:
-Unwanted FIFOs removed
-Latency reduced due to the removal of the FIFOs and a new CRC implementation
-Interface very similar to the one of the Xilinx MAC
This core is in production use.