Go Back

Source code


Name: baudgen
Created: Dec 5, 2007
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009

Other project properties

Category: Communication controller
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
License: GPL


Ever needed a pulse at a given frequency ( period ).
Well that is what BaudGen gives you.
By the use of parameters, you specify the frequency of the clock you wish to divide, the period ( baud rate ) you wish out, and optionally, how fast you want an over sample output.
BaudGen works out the required count values, and outputs one clock wide pulses at the required rate.