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Source code


Name: async_8b10b_encoder_decoder
Created: Dec 19, 2010
Updated: Dec 1, 2011
SVN Updated: Apr 23, 2011

Other project properties

Category: Communication controller
Language: VHDL
Development status: Planning
Additional info:
WishBone Compliant: No
License: LGPL


Usually, 8b/10b codec is required with using a fibre-optic SERDES interface.
A SERDES converts fast serial optic-stream into less fast 10bit parallel electric-signals.
Even though less fast electric-signals, that has almost or more 100Mhz speed.
so the FPGA logic processing 8b/10b must have capable to terminate processing encode and decode with minimal delay.
This project provide you the VHDL code, processing 8b/10b enc/dec asynchronously.
It is implemented by a large lookup-table for better performance.
a lookup-table implementation can offer you with minimal deterministic inter delay.
it can be used with clocked signals also, if you want.
I tested this project with Xilinx XC3S50AN.
Xilinx tools produced the result using just two block-memory within XC3S50AN.
one block-memory is used for an encoder. another block-memory is used for a decoder each.
Oh!. I find my bad..
This project can offer async 8b/10b enc/dec, but not use a block-memory.
a block-memory is needed to shrink logic-gates.
I will change the title of this project soon.