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Source code


Name: single_clock_divider
Created: Apr 23, 2004
Updated: Sep 28, 2011
SVN Updated: Mar 10, 2009

Other project properties

Category: Arithmetic core
Language: VHDL
Development status: Stable
Additional info: Design done , Specification done
WishBone Compliant: No

Before You Read

This is a brief overview of the article about single-clock unsigned integer division algorithm. For comparison and estimation of proposed algorithms please refer to the full article...


Now two division algorithms are wide spread in computing: restoring and non-restoring algorithms. They consider that both algorithms may be used in sequential calculation scheme, when one digit of the result is achieved during one clock. However there are no principle objections against getting all digits of the quotient and the remainder during one clock. So the author tried to develop such kind of algorithm.

Methodology (brief)

Restoring algorithm is seemed to be sequential in nature because during remainder restoring there is positive feedback (A=A – B + B at the same cycle). To avoid the feedback it is necessary to insert register for intermediate result storing. Thus, non-restoring algorithm was chosen as basic for one-clock division algorithm.

Recursive approach was chosen due to it provides compact and transparent description. It is easy to see that synthesis result of the description is sequence of adders.