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Source code


Name: signed_integer_divider
Created: Mar 6, 2013
Updated: Mar 8, 2013
SVN Updated: Mar 6, 2013

Other project properties

Category: Arithmetic core
Language: Verilog
Development status: Alpha
Additional info: Design done , FPGA proven
WishBone Compliant: No
License: LGPL


A divider that calculates the quotient and remainder of a division operation in multiple clock cycles. The dividend, divisor, quotient and remainder are all 32-bit signed integers. By taking the advantage of a shifter that can shift more than one bit (up to 9 bits) during each cycle of computation, it takes less cycles to finish than a radix-2 nonrestoring divider.