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Source code


Name: hcsa_adder
Created: Apr 8, 2003
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009

Other project properties

Category: Arithmetic core
Development status: Stable
Additional info:
WishBone Compliant: No


Hierarchical Carry Save Algorithm (HCSA) is a modification of well known adder algorithm. Comes as VHDL IP core, shows good timing and small area requirements. The Generic HCSA ALU VHDL IP Core presents an example of HCSA methodology. HCSA adder and ALU with HCSA implemented as VHDL soft IP cores. Algorithm implemetation bases on recursion method. Basic Idea: Every Bit of the Result is calculated twice simultaneously : 1. As if there IS NO carry from LSB ( less significant bit ) S(i) = A(i) + B(i) + 0; 2. As if these IS a carry from LSB S(i) = A(i) + B(i) + 1; Real Carry (i-1) used as a Selector for these intermediate sums and precalculated Carry for the next stage (which ones to output). The iteration applies for every bit of the sum. Generic ALU implemented on HCSA method has very good performance/area characteristics due to all Athithmetic operations are made within HCSA module. Logic operations and Command decoder are light weight modules.


- small area requirements for HCSA Adder - 1965 cells ( conditions: 128 bit operands, 0.35u Std Cell Library, typical conditions)
- good performance 6.64ns ( same conditions ).
- flexibility and reusability ( written completely in VHDL, no hardcoded macros used )