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Source code


Name: fpga-median
Created: Mar 18, 2014
Updated: Mar 21, 2014
SVN Updated: Mar 21, 2014

Other project properties

Category: Arithmetic core
Language: Verilog
Development status: Stable
Additional info:
WishBone Compliant: No
License: LGPL


This implementation project proposes a practical implementation of a Median Filter architecture focused in low-cost FPGA devices. The architecture is based on the research presented in the following paper: http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/ENG6530_RCS_html_dr/outline_W2014/docs/PAPER_REVIEW_dr/2013_dr/GRAD_dr/FPGAbasedMedianFilter.pdf
Sorry, but we do not have time to develop a proper architecture document. However the paper presents a brief and at the same time complete description for this implementation design.