Created: Jul 30, 2014
Updated: Jul 31, 2014
SVN Updated: Jul 31, 2014
Other project properties
Development status: Alpha
Additional info: Design done , FPGA proven
WishBone Compliant: No
This is a behavioral module for parallel scrambler/descrambler.
There are RTL scrambler modules available, the purpose of this project is to built a code that is easier to understand and more flexible for reconfiguration. The code is synthesize-able, and should not cost more than RTL modules.