Go Back

Source code


Name: cf_fft
Created: Jan 5, 2003
Updated: May 18, 2012
SVN Updated: Mar 10, 2009

Other project properties

Category: Arithmetic core
Development status: Stable
Additional info:
WishBone Compliant: No


Cores are generated from Confluence ; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent for more info. The Fast Fourier Transform converts time or spacial information into the frequency domain and is one of the most popular DSP algorithms.


The FFT architecture is pipelined on a rank basis; each rank has
its own butterfly and ranks are isolated from each other using
memory interleavers. This FFT can perform calculations on
continuous streaming data (one data set right after another).
More over, inputs and outputs are passed in pairs, doubling the
bandwidth. For instance, a 4096 point FFT can perform a transform
every 2048 cycles.
Each file is stand-alone and represents a specific configuration.
The 2 parameters are:
- Number of Points
- Component (Real/Imag) Precision
All designs are pipelined with a synchronous enable and reset.
The configuration parameters are coded in the file names: cf_fft_4096_18.v
- 4K point FFT.
- 18 bit precision, real and imaginary. Total is 36 bits.
Current configurations:
- cf_fft_256_8
- cf_fft_512_8
- cf_fft_1024_8
- cf_fft_2048_8
- cf_fft_4096_8
- cf_fft_256_16
- cf_fft_512_16
- cf_fft_1024_16
- cf_fft_2048_16
- cf_fft_4096_16
- cf_fft_256_18
- cf_fft_512_18
- cf_fft_1024_18
- cf_fft_2048_18
- cf_fft_4096_18