Created: May 1, 2009
Updated: Jul 25, 2011
SVN Updated: Jul 28, 2011
Other project properties
Development status: Alpha
Additional info: FPGA proven
WishBone Compliant: No
RTL Verilog code to perform Two Dimensional Fast Hartley Transform (2D-FHT) for 8x8 points.
Presented algorithm is FHT with decimation in frequency domain.
Discrete Hartley Transform is used in a wide variety of signal processing applications such as filtering, convolution, correlation, compression and so on.
The most popular usage of the Hartley Transform is image processing applications.
The N-point Discrete Hartley Transform is given by the next formula:
RTL Verilog code which is presented here was designed to calculate 2D-FHT (8x8 points) algorithm with decimation in frequency domain.
This IP was verified using OVM-like verification environment. Main focus was made to compare RTL output data with golden reference model output data.
As a result: RTL is fully identical with golden reference model.
|Xilinx FPGA||Slices||DSP48||BRAM||Freq., MHz|
RTL Verilog release of the Two Dimensional Fast Hartley Transform Algorithm.
Verilog RTL - 1st version released. Refer to repository for latest revision.
Verification - If you have any question please feel free to send me message.
Testbench - If you have any question please feel free to send me message.
Documentation - If you have any question please feel free to send me message.