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Source code


Name: video_stream_scaler
Created: Feb 21, 2011
Updated: Aug 7, 2012
SVN Updated: Feb 25, 2011

Other project properties

Category: Video controller
Language: Verilog
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
License: LGPL


The Video Stream Scaler scales streaming video up or down in resolution. Bilinear and nearest neighbor resize
modes are supported.
This core provides run-time adjustment of input and output resolution, scaling factors, and scale
type. Compile time adjustment of maximum resolutions and data width.

Resource usage and speed

FPGA: Altera Cyclone III 3C120
Configuration: 10 bits per pixel, 1 color channel, RFIFO size of 3
Logic Cells: 571
Registers: 237
M9ks: 9
9x9 multipliers: 3
18x18 multipliers: 8

Greater than 108MHz (SXGA 60Hz) maximum clock rate on Altera Cyclone III 3C120, speed grade 7, 19% total logic element utilization.