Go Back

Source code


Name: lcd_controller
Created: Oct 8, 2004
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009

Other project properties

Category: Video controller
Language: Verilog
Development status: Planning
Additional info: FPGA proven
WishBone Compliant: No
License: GPL


- Display one repeat line (800 pixels) stored in ROM synthesized in FPGA.
- Self-display word block (designed).
- (Have problem on hardware integration) Preparing display a frame stored in SSRAM which is on Logic Module.
- Parameter:
- VBP/VFP (Vertical-Sync. back/front porch)
- HBP/HFP (Horizontal-Sync. back/front porch)
- PPL/LPP (Pixel Per Line/Line Per Panel)
- I design the width of synchronization to be auto-calculated by the way of how it display.
- Improve:
- Efficiency of data transformation.
- Support more kinds of display.
- ..to be continued
- Decrease:
- Needed size of frame buffer.
- Chip area.
- ..to be continued


\http://www.altera.com/products/devices/apex/overview/apx-overview.html#1.8 (EP20K1000E 1.8V)>
- Typical Gates 1 million
- Maximum System Gates 1,771,520
- Logic Elements (LEs) 38,400
- Maximum RAM Bits 327,680 = 40KB
- Phase-Locked Loops (PLLs) 4
- Speed Grades -3, -2, -1 (-1 is the fastest speed grade.)
- Maximum User I/O Pins 708
- Product name TX18D16VM1CAA
- Effective Display Area (H)152.4 x (V)91.44 [mm]
- Display Dots (H)(800x3) x (V)480 [dots]
- (Display Pixels) (H 800 x V 480) [pixels]
- Pixel Pitch (H)0.1905 x (V)0.1905 [mm]
- Color Pixel Arrangement R+G+B Vertical Stripe
- Display Mode Transmissive Mode, Normally White Mode
- Surface Polarizing Film Polarizing Film with Antiglare Coating
- Number of Colors 262k [colors]
- Interface C-MOS, R.G.B x 6 bit Digital each
- Color Saturation 60%(typ) for NTSC
- Viewing Angle 12 o'clock. (The direction it's hard to be discolored)
- Backlight CCFL, 1pc Side-light type (U shape)
- Dimensions Outline (H)165.0(typ) x (V)106.0(typ) x (t)10.5(max) [mm]
- Weight Approximately 170 [g]
..to be continued

Index of specification

- The presentation of this project is in the download field.
- http://www.arm.com/products/solutions/AMBA_Spec.html (AMBA Specification Rev2.0)
- http://www.arm.com/pdfs/DDI0169B_AHB_CPU.pdf (ARM920T AHB Wrapper)
- http://www.arm.com/pdfs/DDI0236F_ssmc_pl093_r0p3_trm.pdf (PrimeCell™ Synchronous Static Memory Controller [PL093] Revision: r0p3)
- http://www.arm.com/products/DevTools/IntegratorFamily.html (RealView Integrator Family)
- http://www.arm.com/products/DevTools/IntegratorAP.html (ASIC Development Platform)
- http://www.arm.com/miscPDFs/5364.pdf (Part Numbers: INAP1-BD-0109A)
- http://www.arm.com/pdfs/DUI0098B.zip (AP User Guide)
- http://www.arm.com/products/DevTools/IntegratorCM920T.html (ARM920T Core Module - No ETM)
- http://www.arm.com/miscPDFs/5364.pdf (Part Numbers: CM920-BD-0113C)
- http://www.arm.com/pdfs/CM920T%20User%20Guide%20.pdf (Core Module User Guide)
- http://www.arm.com/support/integrator_faq.html (Frequently Asked Questions)
- http://www.arm.com/products/DevTools/IntegratorLM-EP20K1000E.html (Altera Apex EP20K1000E Logic Module)
- http://www.arm.com/pdfs/DUI0146C_LM600.pdf (Logic Module User Guide)
- http://www.arm.com/products/DevTools/MultiICE.html (RealView Multi-ICE)
- http://www.arm.com/pdfs/DUI0048F_MICE2_2.pdf (Multi-ICE User Guide)
- http://www.arm.com/pdfs/DUI0154B_MICE_2_2_TapOp.pdf (Multi-ICE TAPOp API Reference Guide)
- http://www.arm.com/support/multi_ice_faq.html (FAQ of Multi-ICE)
- http://hitachi-displays-eu.com/faqs/plist2.asp?moc=colour&sor=screensize&val=%207.0" (Hitachi 7" Colour TFT-LCD Panel with Inverter)
- http://hitachi-displays-eu.com/faqs/pinfo2.asp?pno=TX18D16VM1CAA (TX18D16VM1CAA)
..to be continued