Go Back

Source code


Name: rtftextcontroller
Created: Sep 6, 2011
Updated: Jun 27, 2014
SVN Updated: Jun 25, 2014

Other project properties

Category: Video controller
Language: Verilog
Development status: Beta
Additional info: FPGA proven
WishBone Compliant: Yes
License: LGPL


The latest incarnation of the text controller has a default resolution of 56x31 expecting a 1366x768 screen resolution. The size and number of characters displayed is easily programmable. The controller now uses externally supplied horizontal and vertical sync signals for a reference point. The controller detects the positive edge of the signals. The display memory is 32 bits wide of which 9 bits are used for each of foreground, background colors, and the character code. Character codes and attributes are stored together in the same memory word. The register set for the controller remains the same. There is no longer a separate attribute memory at $FFD1xxxx. Also supported is a transparent color which allows text to be placed ontop of another externally supplied image.
This is a text mode video controller that supports color. The default resolution is 52x31 expecting a 1680x1050 graphics mode for display. The controller uses an external sync generator which must supply end-of-scanline and end-of-frame signals. Display memory is sixteen bits wide of which nine bits are implemented allowing 512 different characters to be displayed simultaneously.
Character bitmaps are stored in block RAM allowing them to be reprogrammed at run time, these can be pre-initialized in a constraints file.
The display controller fits into a memory map at addresses $FFD0xxxx, $FFD1xxxx, and $FFD2xxxx, for the text memory, attribute memory, and character bitmaps respectively.
Note that there are multiple images of the memories within the address range.
The display controller register set is at $FFDA00xx.