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Source code


Name: jpeg
Created: Jan 3, 2005
Updated: May 9, 2014
SVN Updated: Mar 10, 2009

Other project properties

Category: Video controller
Language: VHDL
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No


This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V1000-4 @ 40 MHz). IMAGE RESOLUTION IS LIMITED TO 352x288. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image with headers. A testbench has been made that takes a bitmap image from your computer and writes a compressed JPEG file by simulating the code. In order to be able to run the project you must first generate the RAM/ROM cores and the DCT2D core with Xilinx CoreGen. The configuration values are listed at the bottom of the file compressor.vhd. If you run into any problems downloading the files from the cvs please check that you are downloading them in binary form. For any questions my email is: victor.lopez [(at)] ono [(dot)] com PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.


- JPEG (ISO standard compliant)
- Baseline DCT
- Huffman Encoding
- JFIF Header
- Three quantization (compression) levels
- Hardware resources
- Xilinx Coregen DCT core (2D Forward DCT, needs to be generated)
- Total BlockRAMs: 11
- Total LUTs: 3969 (38% of XC2V1000-4)
- Clock Freq: 41.2 MHz for XC2V1000-4