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Source code


Name: graphicsaccelerator
Created: May 16, 2011
Updated: May 20, 2011
SVN Updated: May 17, 2011

Other project properties

Category: Video controller
Language: VHDL
Development status: Beta
Additional info: Design done , FPGA proven
WishBone Compliant: No
License: LGPL


This project is a group of hardware units that perform graphics algorithms.
For testing purposes, beside the Units that perform these algorithms, there is a Frame Buffer that holds the image drawn and a Video Controller that outputs the image to a screen. In addition to the user interface which consists of switches and push buttons that selects the color, position, function performed, .. etc.

Current State

Till now we have the Bresenham Line Drawing Algorithm.
Due to the Limitations of the FPGA that I am working on, the Frame Buffer is only 170x120 pixels x 8 Colors.


This video shows a test for using the current project where I write my name using Lines with different colors.