Created: Aug 6, 2010
Updated: Aug 7, 2010
SVN Updated: Aug 24, 2010
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
This core is part of the
, the most advanced open source SoC for interactive multimedia applications.
- Minimal VGA framebuffer core
- RGB565 16bpp
- Directly drives a 3x8-bit DAC and sync signals.
- Fully configurable timings and resolution
- Multiple buffering support with buffer switch during the blanking interval to prevent tearing artifacts.
- Milkymist CSR and FML bus interfaces.
- Two asynchronous clock domains - VGA and system.
- Bit-banged DDC interface.
- Core documentation
- CSR bus specifications
- FML bus specifications