Created: May 13, 2014
Updated: Feb 19, 2015
SVN Updated: Mar 11, 2015
Other project properties
Testing / Verification
Development status: Beta
WishBone Compliant: No
The project is intended for checking FPGA-based device for high consumption power.
Number of parameter gives possibility to change number of used LC/DFF, DSP, RAM and I/O.
It can operate at 200 MHz in Cyclone 5E FPGA.
1 LC core is about 1500 LUT4/FF (with default parameters)
1 DSP core is 7 DSP 18*18.
Each LC core also demands 4*N RAM blocks (32 bits width).
To maximize power consumption:
1) Find parameters for maximum FPGA resource usage
2) Fed maximum frequency clock to CLK input (directly or via PLL instantiated in top level)
3) Fed random data to inputs (lower ADC bits or data from PRBS generator)
4) Connect maximal outputs count. Be careful: They are switching simultaneously.
**** USE HIGH LOAD PROJECT AT YOUR OWN RISK ****